CMOS image sensors are beginning to replace conventional CCD sensors for applications requiring image pick-up such as digital cameras, cellular phones, PDA (personal digital assistant), personal computers, and the like. Advantageously, CMOS image sensors are fabricated by applying present CMOS fabricating process for semiconductor devices such as photodiodes or the like, at low costs. Furthermore, CMOS image sensors can be operated by a single power supply so that the power consumption can be restrained lower than that of CCD sensors, and further, CMOS logic circuits and like logic processing devices are easily integrated in the sensor chip and therefore the CMOS image sensors can be miniaturized.
Current CMOS image sensors comprise an array of pixel sensor cells, which are used to collect light energy and convert it into readable electrical signals. Each pixel sensor cell comprises a photosensitive element, such as a photodiode, photo gate, or photoconductor overlying a doped region of a substrate for accumulating photo-generated charge in an underlying portion thereof. A read-out circuit is connected to each pixel cell and often includes a diffusion region for receiving charge from the photosensitive element, when read-out. Typically, this is accomplished by a transistor device having a gate electrically connected to the floating diffusion region. The imager may also include a transistor, having a transfer gate, for transferring charge from the photosensitive element to the floating diffusion region, and a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transfer.
As shown in FIG. 1, a typical CMOS pixel sensor cell 10 includes a pinned photodiode 20 having a pinning layer 18 doped p-type and an underlying collection well 17 lightly doped n-type. Typically, pinned photodiode 20 is formed on top of a p-type substrate 15, or a p-type epitaxial layer or p-well surface layer, having a lower p-type concentration than pinning layer 18. N region 17 and p region 18 of photodiode 20 are typically spaced between an isolation region 19 and a charge transfer transistor gate 25 which is surrounded by thin spacer structures 23a,b. The photodiode 20 thus has two p-type regions 18 and 15 having a same potential so that the n region 17 is fully depleted at a pinning voltage (Vp). The pinned photodiode 20 is termed “pinned” because the potential in the photodiode 20 is pinned to a constant value, Vp, when the photodiode 20 is fully depleted. In operation, light coming from the pixel is focused down onto the photodiode and electrons collect at the n type region 17. When the transfer gate structure 25 is operated, i.e., turned on, the photo-generated charge 24 is transferred from the charge accumulating lightly doped n-type region 17 via a transfer device surface channel 16 to a floating diffusion region 30 which is doped n+ type.
A problem with these current CMOS imaging cells with a charge transfer gate 25 (e.g., a “4 Transistor” cell) is the definitional problem of controlling the readout of the charge. The p-type surface pinning layer 18 is necessary for low dark current, but can create a potential barrier between the n-type charge collection well 17 and the transfer device channel 16. The structure as currently practiced by the industry is also very sensitive to normal manufacturing process variations. Overlay and image size variation of the block masks is critical for cell operation.
For example, in conventional processes for fabricating the pinning layer 18 and collection well 17 in the prior art pixel sensor cell 10 shown in FIG. 1, a problem is that an end portion of the pinning layer 18 and an end portion of the collection well 17 are formed substantially aligned to each other (i.e. identified in FIG. 1 by edge 50) and somewhat overlap the transfer gate structure 25. The pinning layer 18 creates a relatively large potential barrier to charge transfer between the collection well 17 and the transfer device channel 16.
Prior art teaches the use of oblique-rotating implantation or the use of excessive thermal diffusion to position or move the n-type collection well dopant under the transfer gate structure 25 to minimize the potential barrier. U.S. Pat. No. 6,660,553 describes a method whereby an implant mask is used to form a collection well which is partly situated under the transfer gate structure. These conventional processes result in variations in the concentration distribution of the impurity dopant in the n-type collection well which can adversely affect the properties of the photodiode. Also, if the collection well overlaps the transfer gate structure too much, the transfer gate device will suffer from short channel effects. This effects the charge transfer efficiency of the transfer gate device which in turn may degrade performance of the CMOS image sensor.
Structures and methods that minimize the potential barrier created by the pinning layer and the parametric variability of the transfer gate are of great value for image sensors.
It would thus be highly desirable to provide a novel pixel sensor cell and method of manufacture whereby a potential barrier between the charge collection well and the transfer gate channel is reduced without adversely affecting the performance of the photodiode and the transfer gate.